The present invention relates generally to memory and in particular to floating body memory structures.
So-called floating body memory, e.g., floating body dynamic random access memory (FB-DRAM) generally comprises an array of floating body memory cells. A floating body cell is typically formed from a MOSFET (metal oxide semiconductor field effect transistor) disposed atop an insulator such as with silicon on insulator (SOI) type processes or bulk processed chips with separately added insulator areas. An FB cell uses the so-called “history” effect where some of the charge conducted through a transistor having a floating body is retained in the body like a capacitor. The amount of retained charged is affected by different parameters such as the quality of the insulator insulating the body, the amount of body field strength bias, and of course, the amount of charge conducted through it, which is a function of the transistor′s threshold voltage, along with the applied gate and drain/source voltages.
FIG. 1a shows a portion of a conventional layout for a dynamic random access memory (DRAM) array such as for a floating body cell DRAM. Illustrated are active strips 102 (102A to 102C), bit line conductor strips 104 (104A to 104c), wordline conductor strips 106 (106 to 106F), conductive source lines 108 (108A to 108C), conductive traces 110 and vias 111, to accommodate transistor cells. The active areas 102 comprise the channel conduction terminals (sources, drains), along with the bodies, which have at least a portion between the conduction terminals to form the channels when suitably biased. (A portion of the body between the source and drain forms a channel to conduct charge carriers between the source and drain when the gate is sufficiently biased. If the gate is so biased and a sufficient potential is dropped across the channel, depending on the direction of the potential, then a ′1 or a ′0 will be written into it. It should be appreciated that as FETs are typically symmetrical devices, either of the channel conduction terminals may be the source or drain, depending on how they are biased.)
For each transistor, a first channel conduction terminal (e.g., drain) is coupled to a bit line 104 by way of a via 111 and conductor 110; a second channel conduction terminal (e.g., source) is coupled to a source line 108; and the gate is coupled to a wordline conductor strip 106. In this layout, vertically adjacent transistors share common source lines, and vertically aligned cells share a common bit line 104. Also in this depiction, the source lines are coupled to a fixed supply reference (e.g., ground), while the bit lines and wordlines are addressable.
With reference to FIG. 1B, in this depiction, the FB cells use a relatively high bit line (BL) bias to assert (e.g., write a data ′1 into) or erase (write a data ′0 into) a cell using impact ionization. (Note that the terms: erase and assert are arbitrarily assigned ′0 and ′1, respectively, and could be reversed.) In particular, if a selected cell is erased, then a −2.0 V potential is dropped across the bit and source lines. Conversely, if a cell is to be asserted, then a 2.0 V potential is dropped across the bit and source lines.
FIG. 1B shows applied voltage levels for the channel conduction and gate terminals, along with the body, of four neighboring transistors (T1 to T4) from FIG. 1A. (Note that the body is not directly coupled to a bias voltage but rather is exposed to a corresponding field from the insulator, e.g., below it, which is biased and acts like a capacitor.) During programming, selected cells to be programmed (word line selected, T2 and T4 in this figure) are programmed by the bit line, which causes either a positive or negative 2.0 V potential to be dropped across the bit and source lines, depending, respectively, on whether a ′1 or ′0 is to be programmed into the cell.
Unfortunately, with this configuration, cells such as T1 and T3 that are vertically aligned with and neighbor a selected cell also have their channels exposed to write potentials of −2.0 or 2.0 V. Due to the effects of gate induced drain leakage (GIDL), this can cause their data to be flipped or otherwise lost, even though their gates are not selected.